SI5380 Datasheet, PDF (24/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Si5380 test configuration 1: 4 x 3.3 V LVPECL outputs enabled @122.88 MHz, 2 x 3.3 V LVDS outputs enabled @122.88 MHz,
one input enabled, locked to 30.72 MHz. Excludes power in termination resistors.
2. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is
not available. All EVBs support detailed current measurements for any configuration.
3. Differential outputs terminated into an ac-coupled 100 Ω load.
4. LVCMOS outputs measured into a 6-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5380 Reference Manual for more details on register
settings.
5. V_DDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.
Differential Output Test Configuration
IDDO
OUT
OUTb
0.1 uF
50
100
50
0.1 uF
IDDO
OUT
OUTb
LVCMOS Output Test Configuration
Trace length 5
inches
50
499 Ω
4.7 pF
0.1 mF
56 Ω
50 Ω Scope Input
499 Ω
0.1 mF
50
50 Ω Scope Input
4.7 pF
56 Ω
Table 5.3. Input Clock Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Standard Differential or Single-Ended/LVCMOS—AC-coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Input Frequency Range
f_{IN_DIFF}
Differential
10
—
750
f_{IN_SE}
Single-ended/LVCMOS
10
—
250
Input Voltage Amplitude
V_IN
F_IN < 400 MHz
100
—
3600
400 MHz < F_IN < 750 MHz
225
—
3600
Slew Rate^{1 , 2}
SR
Duty Cycle
DC
Capacitance
C_IN
Pulsed CMOS—DC-coupled (IN0, IN1, IN2, IN3/FB_IN) ³
Input Frequency
f_{IN_CMOS}
Input Voltage Thresholds
V_IL
V_IH
Slew Rate^{1 , 2}
SR
Duty Cycle
DC
Minimum Pulse Width
PW
Input Resistance
R_IN
REFCLK (applied to XA/XB)
Clock Input
Pulse Input
400
—
—
40
—
60
—
2
—
10
—
250
–0.2
—
0.33
0.49
—
—
400
—
—
40
—
60
1.6
—
—
—
8
—
Unit
MHz
MHz
mVpp_se,
mVpp_dif
mVpp_se,
mVpp_dif
V/µs
%
pF
MHz
V
V
V/µs
%
ns
kΩ
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