SI5380 Datasheet, PDF (29/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5380 Reference Manual for more details on register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the DC test configuration
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
AC Output Test Configuration
IOL/IOH
IDDO
Zs
OUT
OUTb
VOL/VOH
Trace length 5 inches
50
50
499 Ω
4.7 pF
499 Ω
4.7 pF
0.1 mF
56 Ω
50 Ω Scope Input
0.1 mF
56 Ω
50 Ω Scope Input
Table 5.7. Output Status Pin Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Status Output Pins (LOLb, INTRb)
Output Voltage
V_OH
I_OH = –2 mA
V_DDIO1 x
—
—
V
0.75
V_OL
I_OL = 2 mA
—
—
V_DDIO1 x
V
0.15
Note:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. See the Si5380 Reference Manual for more details
on the register settings.
Parameter
PLL Loop Bandwidth Programming
Range³
Initial Start-Up Time
PLL Lock Time
Output Delay Adjustment
POR to Serial Interface Ready¹
Jitter Peaking
Table 5.8. Performance Characteristics
Symbol
f_BW
t_START
t_ACQ
t_DELAY2
t_RANGE2
t_RDY
J_PK
Test Condition
Min
Loop bandwidth is register
0.1
programmable
Time from power-up or de-as- —
sertion of PDNb to when the
device generates free-running
clocks.
Fastlock enabled⁴
—
t_DELAY= 1/f_VCO
—
+/-128 / f_VCO
—
—
When locked, any loop band-
—
width
Typ
40
30
500
67.8
±8.6
—
—
Max
100
45
600
—
—
15
0.1
Unit
Hz
ms
ms
ps
ns
ms
dB
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