SI5380 Datasheet, PDF(14/50 Page) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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SI5380 Datasheet, PDF (14/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

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Si5380 Data Sheet

Functional Description

3.4.6 LOL Detection

A loss of lock (LOL) monitor asserts the LOL bit when the DSPLL has lost synchronization with the selected input clock. There is also a

dedicated active-low LOLb pin which reflects the loss of lock condition. The LOL monitor measures the frequency difference between

the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set)

and another that clears the indicator (LOL Clear). A block diagram of the LOL monitor is shown in the figure below. The live LOL regis-

ter always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current

state of the LOL monitor.

LOL Monitor

LOL

Clear

LOL

Set

Timer

RS Latch

Reset

Set

LOL

DSPLL

fIN

PD LPF

Feedback

Clock

Ã·M Ã·5

Sticky

LLOOLL

Live

LOLb

Si5380

Figure 3.11. LOL Status Indicators

Each of the frequency monitors have adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. Having two sepa-

rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica-

ted when there is less than 0.2 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is more

than 2 ppm frequency difference is shown in the figure below.

LOL

LOCKED

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

Hysteresis

Lost Lock

0.2

Phase Detector Frequency Difference (ppm)

Figure 3.12. LOL Set and Clear Thresholds

20000

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely phase lock to

the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisi-

tion. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calcula-

ted using the ClockBuilder Pro utility.

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