SI5380 Datasheet, PDF (5/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Functional Description
Fin (MHz)¹
LTE Device Clock Frequencies Fout (MHz)²
Note:
1. The Si5380 locks to any one of the frequencies listed in the Fin column and generates LTE device clock frequencies.
2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.
3.1.2 Si5380 Configuration for JESD204B Clock Generation
The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete
VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks
(DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF
clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or
more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS-
REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica-
tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example
of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency
and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in-
cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device
clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4),
though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the
3.5.15 Output Skew Control (Δt₀ - Δt₄) section for details on skew control. The SYSREF clock is always periodic and can be controlled
(on/off) without glitches by enabling or disabling its output through register writes.
IN_SEL[1:0]
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
Si5380
÷P0
÷P1
DSPLL
÷P2
PD LPF
÷P3
÷M ÷5
÷N0 t0
÷R0A
÷R0
÷R5
÷R6
÷R7
÷R8
÷R9
÷R9A
÷N1 t1
÷R1
÷N2 t2
÷R2
÷N3 t3
÷R3
÷N4 t4
÷R4
VDDO0
OUT0A
OUT0Ab
OUT0
OUT0b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
Device
Clocks
OUT9
OUT9b
OUT9A
OUT9Ab
VDDO9
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
SYSREF
Clocks
Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks
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