SI5380 Datasheet, PDF (10/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Data Sheet
Functional Description
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN)
An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection
criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by
the automatic state machine. If there are no valid references available, the DSPLL will enter the holdover mode. With revertive switch-
ing enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an
automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is
valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated.
3.3.4 Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency
locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies
are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each
other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input
switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined
by the DSPLL loop bandwidth.
3.3.5 Glitchless Input Switching
The DSPLL has the ability of switching between two input clocks that are up to 200 ppm apart in frequency. The DSPLL will pull-in to
the new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indica-
tor will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the out-
put. Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled.
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