SI5380 Datasheet, PDF (41/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Pin Name
SDA/SDIO
Pin Number
18
A1/SDO
17
SCLK
16
A0/CSb
19
Control/Status
INTRb
12
PDNb
5
RSTb
6
OEb
11
LOLb
47
SYNCb
48
silabs.com | Smart. Connected. Energy-friendly.
Pin Type¹
I/O
I/O
I
I
O
I
I
I
O
I
Si5380 Data Sheet
Pin Description
Function
Serial Data Interface. This is the bidirectional da-
ta pin (SDA) for the I²C mode, the bidirectional da-
ta pin (SDIO) in the 3-wire SPI mode, or the input
data pin (SDI) in 4-wire SPI mode. When in I²C
mode or unused, this pin must be pulled-up using
an external resistor of at least 1 kΩ. No pull-up re-
sistor is needed when in SPI mode. This pin is 3.3
V tolerant.
Address Select 1/Serial Data Output. In I²C
mode this pin functions as the A1 address input
pin. In 4-wire SPI mode, this is the serial data out-
put (SDO) pin. This pin is 3.3 V tolerant. This pin
must be pulled-up externally when unused.
Serial Clock Input. This pin functions as the seri-
al clock input for both I²C and SPI modes. When
in I²C mode or unused, this pin must be pulled-up
using an external resistor of at least 1 kΩ. No pull-
up resistor is needed when in SPI mode. This pin
is 3.3 V tolerant.
Address Select 0/Chip Select. This pin functions
as the hardware controlled address A0 in I²C
mode. In SPI mode, this pin functions as the chip
select input (active low). This pin is internally
pulled-up. This pin is 3.3 V tolerant.
Interrupt. ² This pin is asserted low when a
change in device status has occurred. This pin
must be pulled-up externally using a resistor of at
least 1 kΩ. It should be left unconnected when not
in use.
Power Down. ² The device enters into a low pow-
er mode when this pin is pulled low. This pin is in-
ternally pulled-up. This pin is 3.3 V tolerant. It can
be left unconnected when not in use.
Device Reset. ² Active low input that performs
power-on reset (POR) of the device. Resets all in-
ternal logic to a known state and forces the device
registers to their default values. Clock outputs are
disabled during reset. This pin is internally pulled-
up. This pin is 3.3 V tolerant.
Output Enable. ² This pin disables all outputs
when held high. This pin is internally pulled low
and can be left unconnected when not in use. This
pin is 3.3 V tolerant.
Loss Of Lock. ² This output pin indicates when
the DSPLL is locked (high) or out-of-lock (low).
When in use, this pin must be pulled-up using an
external resistor of at least 1 kΩ. It can be left un-
connected when not in use.
Output Clock Synchronization. ² An active low
signal on this pin resets the output dividers for the
purpose of re-aligning the output clocks. This pin
is internally pulled-up and can be left unconnected
when not in use.
Rev. 0.96 | 40