SI5380 Datasheet, PDF (40/50 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Pin Name
IN3/FB_IN
IN3b/FB_INb
Outputs
OUT0A
OUT0Ab
OUT0
OUT0b
OUT1
OUT1b
OUT2
OUT2b
OUT3
OUT3b
OUT4
OUT4b
OUT5
OUT5b
OUT6
OUT6b
OUT7
OUT7b
OUT8
OUT8b
OUT9
OUT9b
OUT9A
OUT9Ab
Serial Interface
I2C_SEL
Pin Number
61
62
21
20
24
23
28
27
31
30
35
34
38
37
42
41
45
44
51
50
54
53
56
55
59
58
39
Pin Type¹
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Si5380 Data Sheet
Pin Description
Function
Clock Input 3/External Feedback Input.
By default, these pins are used as the 4th clock in-
put (IN3/IN3b). They can also be used as the ex-
ternal feedback input (FB_IN/FB_INb) for the op-
tional zero delay mode. See section 5.3.6 for de-
tails on the optional zero delay mode.
Output Clocks. These output clocks support pro-
grammable signal amplitude and common mode
voltage. Desired output signal format is configura-
ble using register control. Termination recommen-
dations are provided in the sections, 3.5.4 Differ-
ential Output Modes and 3.5.6 LVCMOS Output
Terminations. Unused outputs should be left un-
connected.
I2C Select. This pin selects the serial interface
mode as I²C (I2C_SEL = 1) or SPI (I2C_SEL = 0).
This pin is internally pulled high.
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Rev. 0.96 | 39