SI5348 Datasheet, PDF (7/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.5.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC)
Controlling the output frequency with pin controls is available. This feature involves asserting the FINC or FDEC pins to step (increment
or decrement) the DSPLL’s output frequency. Both the step size and DCO selection (A, C, D) is made through the serial interface by
writing to register bits.
Si5348
FINC
FDEC
0x001D
I2C_SEL
SDA/SDIO
A1/SDO
SCLK
A0/CSb
SPI/
I²C
FSW_MASK_A
0x0422
FSW_MASK_C
0x0622
FSW_MASK_D
0x0723
PD LPF
÷
Mn_A
Md_A
DSPLL A
+ Frequency
- Step Word
0x0423 – 0x0429
PD LPF
÷
Mn_C
Md_C
DSPLL C
+ Frequency
- Step Word
0x0623 – 0x0629
PD LPF
÷
Mn_D
Md_D
DSPLL D
+ Frequency
- Step Word
0x0724 – 0x072A
Figure 3.3. Controlling the DCO Mode By Pin Control
3.5.2 Frequency Increment/Decrement Using the Serial Interface
Controlling the DSPLL frequency through the serial interface is available. This feature involves asserting the FINC or FDEC bits to acti-
vate the frequency change defined by the frequency step word. A set of mask bits selects the DSPLL(s) that is affect by the frequency
change.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 6