SI5348 Datasheet, PDF (18/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.9.2 Support For 1 Hz Output
Output 6 of the Si5348 can be configured to generate a 1 Hz clock by cascading the R5 and R6 dividers. Output 5 is still usable in this
case but is limited to a maximum frequency of 33.5 MHz. ClockBuilder Pro automatically determines the optimum configuration when
generating a 1 Hz output (1 PPS).
A
C
÷R4
D
VDDO4
OUT4
OUT4b
A
C
÷R5
D
VDDO5
OUT5
OUT5b
R5
A
C
÷R6
D
VDDO6
OUT6
OUT6b
Figure 3.18. Generating a 1 Hz Output using the Si5348
3.9.3 Differential Output Terminations
Note: In this document, the terms LVDS and LVPECL refer to driver formats that are compatible with these signaling standards.
The differential output drivers support both ac-coupled and dc-coupled terminations, as shown in the figure below:
DC-coupled LVDS
VDDO = 3.3V, 2.5V, 1.8V
OUTx
50
OUTxb
50
Si5348
AC-coupled HCSL
VDDO = 3.3V, 2.5V, 1.8V
R1
R1
Si5348
OUTx
50
OUTxb
50
R2
R2
For VCM = 0.35 V
VDDRX
3.3 V
2.5 V
1.8 V
R1
442 Ω
332 Ω
243 Ω
R2
56.2 Ω
59 Ω
63.4 Ω
100
VDDRX
AC-coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
OUTx
50
OUTxb
100
50
Si5348
Internally
self-biased
Standard
HCSL
Receiver
VDDO = 3.3V, 2.5V
AC-coupled LVPECL
VDD – 1.3V
50
50
Si5348
OUTx
50
OUTxb
50
Figure 3.19. Supported Differential Output Terminations
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 17