SI5348 Datasheet, PDF (20/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.9.10 Output Enable/Disable
The Si5348 allows enabling/disabling outputs by pin or register control, or a combination of both. Three output enable pins are available
(OE0b, OE1b, OE2b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default
OE0b controls all of the outputs while OE1b and OE2b remain unmapped and has no effect until configured. The figure below shows an
example of an output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up.
Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s)
has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control.
Si5348
Output
Crosspoint
Si5348
Output
Crosspoint
DSPLL
A
DSPLL
C
A
C
÷R0
D
A
C
÷R1
D
A
C
÷R2
D
A
C
÷R3
D
A
C
D
÷R4
OUT0
OUT0b
OUT1
OUT1b
OUT2
OUT2b
OUT3
OUT3b
OUT4
OUT4b
DSPLL
D
A
C
÷R5
D
OUT5
OUT5b
R5
A
C
÷R6
D
OUT6
OUT6b
OE0b
OE1b
OE2b
In its default state the OE0b pin enables/disables all
outputs. The OE1b and OE2b pins are not mapped
and have no effect on outputs.
DSPLL
A
DSPLL
C
A
C
÷R0
D
A
C
÷R1
D
A
C
÷R2
D
A
C
÷R3
D
A
C
D
÷R4
OUT0
OUT0b
OUT1
OUT1b
OE0b
OUT2
OUT2b
OUT3
OUT3b
OE1b
OUT4
OUT4b
DSPLL
D
A
C
÷R5
D
R5
A
C
÷R6
D
OUT5
OUT5b
OUT6
OUT6b
OE2b
An example of a configurable output enable scheme. In
this case OE0b controls the outputs associated with DSPLL
A, OE1b controls the outputs for DSPLL C, and OE2b
controls the outputs for DSPLL D.
Figure 3.21. Example of Configuring Output Enable Pins
3.9.11 Output Disable During LOL
By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to
disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.9.12 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during asser-
tion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy
and stability will be indeterminate during this fault condition.
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