SI5348 Datasheet, PDF (44/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Pin Name¹
SDA/SDIO
Pin Number
18
A1/SDO
17
SCLK
16
A0/CSb
19
Control/Status
INTRb
12
RSTb
6
OE0b
11
OE1b
26
OE2b
27
LOL_Ab⁴
21
LOL_Cb³
3
LOL_Db³
28
LOS0b⁴
20
LOS1b³
47
LOS2b³
55
FDEC
25
FINC
48
Pin Type ²
I/O
I/O
I
I
Si5348 Rev D Data Sheet
Pin Descriptions
Function
Serial Data Interface³. This is the bidirectional data pin (SDA) for the I²C
mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the
input data pin (SDI) in 4-wire SPI mode. When not in SPI mode, this pin
must be pulled-up using an external resistor of at least 1 kΩ. No pull-up
resistor is needed when in SPI mode unless the master SPI driver is open
drain. This pin is 3.3 V tolerant.
Address Select 1/Serial Data Output³. In I²C mode this pin functions as
the A1 address input pin and does not have an internal pull up or pull
down resistor. In 4-wire SPI mode, this is the serial data output (SDO)
pin. and drives high to the voltage selected by the IO_VDD_SEL pin. This
pin is 3.3 V tolerant. This pin must be pulled up externally when unused.
Serial Clock Input³. This pin functions as the serial clock input for both
I²C and SPI modes. This pin does not have an internal pull-up or pull-
down. When in I²C mode or unused, this pin must be pulled-up using an
external resistor of at least 1 kΩ. No pull-up resistor is needed when in
SPI mode unless the SPI master driver is open drain. This pin is 3.3 V tol-
erant.
Address Select 0/Chip Select³. This pin functions as the hardware con-
trolled address A0 input pin in I²C mode. In SPI mode, this pin functions
as the chip select input (active low). This pin is internally pulled-up by a
20 kΩ resistor to the voltage selected by the IO_VDD_SEL register bit.
This pin is 3.3 V tolerant.
O
Interrupt³. This pin is asserted low when a change in device status has
occurred. It should be left unconnected when not in use.
I
Device Reset³. Active low input that performs power-on reset (POR) of
the device. Resets all internal logic to a known state and forces the de-
vice registers to their default values. Clock outputs are disabled during re-
set. This pin is internally pulled-up.
I
Output Enable 0-2³. These output enable pins have a programmable
I
register mask which allows them to control any of the output clocks. By
default the OE0b pin enables all output clocks and OE1b, OE2b have no
I
control over the output clocks until register configured. These pins are in-
ternally pulled low and can be left unconnected when not in use.
O
Loss of Lock_A/C/D. These output pins indicate when DSPLL A, C, D is
out-of-lock (low) or locked (high). They can be left unconnected when not
O
in use.
O
O
Loss of Signal for IN0, IN1, IN2. These pins reflect the loss of signal
register status bits for inputs (IN0, IN1, IN2). These pins can be left un-
O
connected when not in use.
O
I
Frequency Decrement Pin⁴. This pin is used to step-down the output
frequency of a selected DSPLL. The frequency change step size is regis-
ter configurable. This pin does not have an internal pullup/pulldown and
must be externally pulled when unused.
I
Frequency Increment Pin³. This pin is used to step-up the output fre-
quency of a selected DSPLL. The frequency change step size is register
configurable. The DSPLL(s) affected by the frequency change is deter-
mined by the M_FSTEP_MSK_PLLx register settings. This pin is pulled
low internally and can be left unconnected when not in use.
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