SI5348 Datasheet, PDF (5/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.4.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A
soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs,
while a soft reset can either affect all or each DSPLL individually.
No valid input
clocks available
for selection
Power-Up
Reset and
Initialization
No valid
input clocks
selected
An input is
qualified and
available for
selection
Holdover
Mode
Free-run
Valid input clock
selected
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Input Clock
Switch
Yes
No
Holdover
History
Valid?
Locked
Mode
Selected input
clock fails
Yes _{Other Valid}
Clock Inputs
No ^Available?
Figure 3.1. Modes of Operation
3.4.2 Free-run Mode
Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode. The frequen-
cy accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the clock source at the
reference inputs (REF/REFb). A TCXO or OCXO is recommended for applications that need frequency accuracy and stability to meet
the synchronization standards as shown in the following table:
Table 3.2. Free-run Accuracy for North American and European Synchronization Standards
SONET (Telcordia)
GR-253 Stratum 3E
GR-253 Stratum 3
—
SDH (ITU-T)
G.812 Type III
G.812 Type IV
G.813 Option 1
SyncE (ITU-T)
—
G.8262 EEC Option 2
G.8262 EEC Option 1
Free-run Accuracy
±4.6 ppm
3.4.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.If the fast lock feature is enabled, a DSPLL will acquire lock using
the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. Dur-
ing lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.
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