SI5348 Datasheet, PDF (16/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilderPro utility.
3.8.7 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers.
LOS_FLG 0x0012[0]
IN0
OOF_FLG 0x0012[4]
LOS_FLG 0x0012[1]
IN1
OOF_FLG 0x0012[5]
LOS_FLG 0x0012[2]
IN2
OOF_FLG 0x0012[6]
Si5348
LOS_FLG 0x0011[6]
IN3
LOS_FLG 0x0011[7]
IN4
LOS_FLG 0x0012[3]
REF
LOL_FLG_PLL[B] 0x0013[1]
SYSINCAL_FLG 0x0011[0]
LOSXAXB_FLG 0x0011[1]
SMBUS_TIMEOUT_FLG 0x0011[5]
CAL_FLG_PLL[A] 0x000F[4]
CAL_FLG_PLL[B] 0x000F[5]
CAL_FLG_PLL[C] 0x000F[6]
CAL_FLG_PLL[D] 0x000F[7]
Device
CAL
LOL_FLG_PLL[A] 0x0013[0]
LOL_FLG_PLL[C] 0x0013[2]
LOL_FLG_PLL[D] 0x0013[3]
HOLD_FLG_PLL[A] 0x0013[4]
HOLD_FLG_PLL[C] 0x0013[6]
HOLD_FLG_PLL[D] 0x0013[7]
LOL
HOLD
Figure 3.16. Interrupt Triggers and Masks
INTRb
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