SI5348 Datasheet, PDF (12/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.7.5 Hitless Input Switching
Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that
have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that
they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,
the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-
ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL
basis. Clock inputs 3 and 4 do not support hitless switching.
3.7.6 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.4.5 Hold-
over Mode.
3.7.7 Glitchless Input Switching
The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to
the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indi-
cator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output
during the transition. All clock inputs, including 3 and 4, support glitchless input switching.
3.7.8 Synchronizing to Gapped Input Clocks
Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose
of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely
increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic
clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For exam-
ple, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is
shown in the figure below:
Gapped Input Clock
100 MHz clock
1 missing period every 10
Periodic Output Clock
90 MHz non-gapped clock
100 ns
100 ns
1 2 3 4 5 6 7 8 9 10
10 ns
Period Removed
DSPLL
123456789
11.11111... ns
Figure 3.9. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-
ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the
hitless switching specification in Table 5.8 Performance Characteristics on page 31 when the switch occurs during a gap in either
input clock.
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