SI5348 Datasheet, PDF (11/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.7.4 Input Configuration and Terminations
Inputs IN0-IN2 can be configured as differential or single-ended LVCMOS. Inputs IN3-IN4 are single-ended only. The recommended
input termination schemes are shown in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle
Pulsed CMOS signals can be dc-coupled. Unused inputs can be disabled and left unconnected when not in use.
Standard AC-coupled Differential LVDS (IN0-IN2)
50
3.3 V, 2.5 V
LVDS or
50
CML
INx
100
INxb
Si5348
Standard
Pulsed CMOS
Standard AC-coupled Differential LVPECL (IN0-IN2)
50
3.3 V, 2.5 V
50
LVPECL
INx
100
INxb
Si5348
Standard
Pulsed CMOS
Standard AC-coupled Single-Ended (IN0-IN2)
50
3.3 V, 2.5 V, 1.8 V
LVCMOS
INx
INxb
Si5348
Standard
Pulsed CMOS
Pulsed CMOS DC-coupled Single-Ended
(IN0-IN2)
Si5348
R1
50
INx
Standard
3.3 V, 2.5 V, 1.8 V
LVCMOS
VDD
Resistor values for
fIN_PULSED < 1 MHz
1.8 V
2.5 V
3.3 V
R2
R1 (Ohm) R2 (Ohm)
324
665
511
475
634
365
INxb
Pulsed CMOS
IN3, IN4 – DC-coupled LVCMOS
Si5348
50
INx
Figure 3.8. Termination of Differential and LVCMOS Input Signals
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