SI5348 Datasheet, PDF (27/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Voltage Swing ¹
V_IN
Differential AC-coupled
100
f_IN< 250 MHz
—
1800
mVpp_se
Differential AC-coupled
225
—
1800
mVpp_se
250 MHz < f_IN< 750 MHz
Single-ended AC-coupled
100
—
3600
mVpp_se
f_IN < 250 MHz
Slew Rate^2,3
SR
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Input Capacitance
C_IN
—
0.3
—
pF
Input Resistance
R_IN
—
16
—
kΩ
Pulsed CMOS Input Buffer - DC-coupled (IN0, IN1, IN2)⁴
Input Frequency
f_{IN_PULSED_CM}
OS
0.008
—
250
MHz
Input Voltage
V_IL
–0.2
—
0.4
V
V_IH
0.8
—
—
V
Slew Rate^2,3
SR
400
—
—
V/μs
Duty Cycle
DC
40
—
60
%
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
kΩ
LVCMOS Input Buffer - AC/DC Coupled (IN3, IN4)
Input Frequency
f_{IN_CMOS}
0.008
—
2.048
MHz
Input Voltage⁵
V_IL
–0.2
—
1.2
V
V_IH
2.2
—
—
V
Minimum Pulse Width
PW
Pulse Input
50
—
—
ns
Input Resistance
R_IN
—
20
—
kΩ
Note:
1. Voltage swing is specified as single-ended mVpp.
OUTx
Vcm
Vcm
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 - 0.2) x V_{IN_Vpp_se}) / SR.
4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since
the input thresholds (V_IL, V_IH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for
DC-coupled Pulsed LVCMOS in the Si5348 Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard
AC-coupled, Single-ended input mode.
5. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD.
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 26