SI5348 Datasheet, PDF (28/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Electrical Specifications
Table 5.4. Control Input Pin Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Si5348 Control Input Pins (I2C_SEL, A0/CSb, A1/SDO, SDA/SDIO, SCLK, RSTb, OE0b, OE1b, OE2b, FINC)
Input Voltage
V_IL
—
—
0.3 ×
V_DDIO1
V_IH
0.7 ×
—
—
V_DDIO1
Input Capacitance
C_IN
—
2
—
Input Resistance
R_L
—
20
—
Minimum Pulse Width
PW
RSTb, FINC
100
—
—
Update Rate
F_UR
FINC
—
—
1
Si5348 Control Input Pin (FDEC)
Input Voltage
V_IL
—
—
0.3 × V_DDS
V_IH
0.7 × V_DDS
—
—
Input Capacitance
C_IN
—
2
—
Minimum Pulse Width
PW
FDEC
100
—
—
Update Rate
F_UR
FDEC
—
—
1
Note:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD.
Unit
V
V
pF
kΩ
ns
MHz
V
V
pF
ns
MHz
Parameter
Output Frequency
Duty Cycle
Output-Output Skew
Using Same DSPLL
OUT-OUTb Skew
Output Voltage Amplitude¹
Table 5.5. Differential Clock Output Specifications
Symbol
Test Condition
Min
Typ
f_OUT
0.0001
—
f_OUT1Hz
1 PPS signal only available
1
on Output 6
DC
f_OUT < 400 MHz
48
—
400 MHz < f_OUT < 712.5
45
—
MHz
T_SKS
Outputs on same DSPLL
—
—
(Measured at 712.5 MHz)
T_{SK_OUT}
Measured from the positive
—
0
to negative output pins
V_OUT
V_DDO = 3.3 V,
LVDS
350
430
2.5 V, or 1.8 V _LVPECL
640
750
Max
712.5
52
55
65
Unit
MHz
Hz
%
%
ps
50
ps
510
mVpp_se
900
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 27