SI5348 Datasheet, PDF (2/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

1. Feature List
The Si5348 features are listed below:
• Three independent DSPLLs in a single monolithic IC support-
ing flexible SyncE/IEEE 1588 and SETS architectures
• Ultra-Low Jitter
• 100 fs typ (12 kHz to 20 MHz)
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 & 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any input
frequency
• Input frequency range:
• External crystal: 48-54 MHz
• REF clock: 5-250 MHz
• Diff clock: 8 kHz-750 MHz
• LVCMOS clock: 8 kHz-250 MHz
• Output frequency range:
• Differential: 1 PPS to 712.5 MHz
• LVCMOS: 1 PPS to 250 MHz
Si5348 Rev D Data Sheet
Feature List
• Pin or software controllable DCO on each DSPLL with typical
resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/hold-
over accuracy and stability
• Programmable jitter attenuation bandwidth per DSPLL:
0.001 Hz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,
HCSL, CML
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring: LOS, OOF, LOL
• _{Serial Interface: I}²_{C or SPI (3-wire or 4-wire)}
• _ClockBuilder^TM _{Pro software tool simplifies device configura-}
tion
• 5 input, 7 output, 64 QFN
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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