SI5348 Datasheet, PDF (15/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.8.6 LOL Detection
There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts the LOL register bit when a DSPLL has lost synchronization
with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs
(LOL_Ab, LOL_Cb, LOL_Db) and also for the reference. There are two LOL frequency monitors, one that sets the LOL indicator (LOL
Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow addi-
tional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or
chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL
register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the
current state of the LOL monitor.
Si5348
Sticky
LOL StatuLsORSegisters
Live
LOL Monitor
LOL
Clear
t
LOL
Set
DSPLL D
DSPLL C
DSPLL A
fIN
DSPLL A
PD LPF
÷M
LOL_Db
LOL_Cb
LOL_Ab
Figure 3.14. LOL Status Indicators
Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two
separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is
indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is
more than 1 ppm frequency difference is shown in Figure 3.15 LOL Set and Clear Thresholds on page 14.
LOL
LOCKED
0
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
Hysteresis
Lost Lock
0.1
1
Phase Detector Frequency Difference (ppm)
10,000
Figure 3.15. LOL Set and Clear Thresholds
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