SI5348 Datasheet, PDF (26/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Electrical Specifications
Table 5.2. DC Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Core Supply Current¹
Output Buffer Supply Current
I_DD
I_DDA
I_DDOx
LVPECL Output²
@ 156.25 MHz
LVDS Output²
—
290
460
mA
—
125
145
mA
—
22
26
mA
—
15
18
mA
@ 156.25 MHz
3.3 V LVCMOS³ output
—
22
30
mA
@ 156.25 MHz
2.5 V LVCMOS³ output
—
18
23
mA
@ 156.25 MHz
1.8 V LVCMOS³ output
—
12
16
mA
@ 156.25 MHz
Total Power Dissipation^{1, 4}
P_d
Si5348
—
1250
1600
mW
Note:
1. Si5348 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Differential outputs terminated into an AC coupled 100 Ω load.
3. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV
= 3, which is the strongest driver setting. Refer to the Si5348 Reference Manual for more details on register settings.
4. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not
available. All EVBs support detailed current measurements for any configuration.
Differential Output Test Configuration
IDDO
OUT
OUTb
0.1 uF
50
100
50
0.1 uF
IDDO
OUT
OUTb
LVCMOS Output Test Configuration
Trace length 5
inches
50
499 Ω
0.1 uF
4.7 pF
56 Ω
50 Ω Scope Input
499 Ω
0.1 uF
50
50 Ω Scope Input
4.7 pF
56 Ω
Table 5.3. Input Clock Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Standard Input Buffer (IN0, IN1, IN2, REF)
Input Frequency Range
f_{IN_DIFF}
Differential
0.008
—
Single-ended/LVCMOS
0.008
—
750
MHz
250
REF
5
—
250
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