SI5348 Datasheet, PDF (4/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5348 offers three DSPLLs that have identical performance and flexibility which can be independently configured and controlled
through the serial interface. Each of the DSPLLs support locked, free-run, and holdover modes of operation with an optional DCO mode
for IEEE 1588 applications. The device requires an external crystal and an external reference (TCXO or OCXO) to operate. The refer-
ence input (REF/REFb) determines the frequency accuracy and stability while in free-run and holdover modes. The external crystal
completes the internal oscillator circuit (OSC) which is used by the DSPLL for intrinsic jitter performance. There are three main inputs
(IN0 - IN2) for synchronizing the DSPLLs. Input selection can be manual or automatically controlled using an internal state machine.
Two additional manually selected inputs are available to DSPLL D. Any of the output clocks (OUT0 to OUT6) can be configured to any
of the DSPLLs using a flexible crosspoint connection. Output 6 is the only output that can be configured for a 1 Hz output to support 1
PPS.
3.1 Standards Compliance
Each of the DSPLLs meet the requirements of ITU-T G.8262 (SyncE), G.812, G.813, G.8273.2 (T-BC), in addition to Telcordia
GR-1244 and GR-253 as shown in the compliance report. The DCO feature enables IEEE1588 (PTP) implementations in addition to
hybrid SyncE + IEEE1588 (T-BC).
3.2 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division
(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a
specific frequency plan are easily determined using the ClockBuilder Pro utility.
3.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter and wander attenuation. Register configurable DSPLL loop
bandwidth settings of 1 mHz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
Table 3.1. Loop Bandwidth Requirements for North America
SONET (Telcordia)
GR-253 Stratum 3E
GR-253 Stratum 3
—
SDH (ITU-T)
G.812 Type III
G.812 Type IV
G.813 Option 1
SyncE (ITU-T)
—
G.8262 EEC Option 2
G.8262 EEC Option 1
Loop Bandwidth
0.001 Hz
<0.1 Hz
1 - 10 Hz
3.3.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock
feature can be enabled or disabled independently for each of the DSPLLs.
3.4 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation
on page 4. The following sections describe each of these modes in greater detail.
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