SI5348 Datasheet, PDF (35/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Table 5.10. SPI Timing Specifications (4-Wire)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CSb Rise to SDIO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
Symbol
Min
Typ
f_SPI
—
—
T_DC
40
—
T_C
50
—
T_D1
—
—
T_D2
—
—
T_D3
—
—
T_SU1
5
—
T_H1
5
—
T_SU2
5
—
T_H2
5
—
T_CS
2
—
SCLK
CSb
SDI
SDO
TSU1
TD1
TC
TSU2
TH2
TD2
Figure 5.2. 4-Wire SPI Serial Interface Timing
Si5348 Rev D Data Sheet
Electrical Specifications
Max
Unit
20
MHz
60
%
—
ns
18
ns
15
ns
15
ns
—
ns
—
ns
—
ns
—
ns
—
T_C
TH1
TCS
TD3
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