SI5348 Datasheet, PDF (6/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

Si5348 Rev D Data Sheet
Functional Description
3.4.4 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is
achieved. Refer to 3.8.6 LOL Detection for more details on the operation of the loss of lock circuit.
3.4.5 Holdover Mode
Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input
clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the
disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up
to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calcula-
ted from a programmable window within the stored historical frequency data. Both the window size and delay are programmable as
shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring
frequency data that may be corrupt just before the input clock failure.
Historical Frequency Data Collected
Clock Failure and
Entry into Holdover
time
120s
Programmable historical data window
used to determine the final holdover value
1s,10s, 30s, 60s
Programmable delay
30ms, 60ms, 1s,10s, 30s, 60s
0s
Figure 3.2. Programmable Holdover Window
When entering holdover, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in holdover,
the output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. If the clock input be-
comes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves pulling
the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in process is glitchless.
The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated, the difference be-
tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-
ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40
values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit
from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on
ramped input switching see 3.7.6 Ramped Input Switching.
Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable
holdover exit BW.
3.5 Digitally-Controlled Oscillator (DCO) Mode
The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words
(FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or
decrements (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The
DCO mode is available when the DSPLL is operating in locked mode. The DCO mode is mainly used in IEEE1588 (PTP) applications
where a clock needs to be generated based on recovered timestamps. In this case timestamps are recovered by the PHY/MAC. A pro-
cessor containing servo software controls the DCO to close the timing loop between the master and slave nodes. The processor has
the option of using the FINC/FDEC pin controls to update the DCO frequency or by controlling it through the serial interface.
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