SI5348 Datasheet, PDF(32/54 Page) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

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SI5348 Datasheet, PDF (32/54 Pages) Silicon Laboratories – Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary (T-BC) and Slave (T-SC) Clocks

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Si5348 Rev D Data Sheet

Electrical Specifications

Table 5.8. Performance Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Loop Bandwidth Program-

fBW

ming Range1

0.001

4000

Initial Start-Up Time

tSTART

Time from power-up to

when the device gener-

ates free-running clocks

PLL Lock Time2

tACQ

With Fastlock enabled

280

300

POR to Serial Interface Ready3

tRDY

Jitter Peaking

JPK

Measured with a frequen-

0.1

cy plan running a 25 MHz

input, 25 MHz output, and

a loop bandwidth of 4 Hz

Jitter Tolerance

JTOL

Compliant with G.8262

Options 1&2

3180

UI pk-pk

Carrier Frequency =

10.3125 GHz

Jitter Modulation Frequen-

cy = 10 Hz

Maximum Phase Transient Dur-

tSWITCH

Only valid for a single au-

1.2

ing a Hitless Switch

tomatic switch between

two input clocks at same

frequency

Only valid for a single

manual switch between

two input clocks at same

frequency

0.9

Pull-in Range

ÏP

500

ppm

Input-to-Output Delay Variation

tIODELAY Measured between a com-

1.6

mon 2 MHz input and 2

MHz output with different

DSPLLs on the same unit.

DSPLL BW = 4 kHz

Measured between a com-

mon 2MHz input and 2

MHz output with different

DSPLLs between units.

1.8

DSPLL BW = 4 kHz

RMS Phase Jitter4

JGEN

12 kHz to 20 MHz

100

150

fs rms

Note:

1. Actual loop bandwidth might be lower; refer to CBPro for actual value on your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with fastlock bandwidth set to 100 Hz, LOL set/clear thresholds of 3/0.3 ppm respectively, using IN0 as clock

reference by removing the reference and enabling it again, then measuring the delta time between the first rising edge of the

clock reference and the LOL indicator de-assertion.

3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.

4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL. (Does not include jitter from input reference).

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