HYB39S256400 Datasheet, PDF (8/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity Function
DQM Input
LDQM
UDQM
Pulse Active
High
The Data Input/Output mask places the DQ buffers in a high
impedance state when sampled high. In Read mode, DQM
has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a
latency of zero and operates as a word mask by allowing
input data to be written if it is low but blocks the write
operation if DQM is high.
One DQM input it present in ×4 and ×8 SDRAMs, LDQM and
UDQM controls the lower and upper bytes in ×16 SDRAMs.
V_DD,
Supply –
–
V_SS
V_DDQ Supply –
–
V_SSQ
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
Semiconductor Group
8
1998-10-01