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HYB39S256400 Datasheet, PDF (15/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM
HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Absolute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 °C
Storage temperature range..................................................................................... – 55 to + 150 °C
Input/output voltage .......................................................................................... – 0.3 to VCC + 0.3 V
Power supply voltage VDD / VDDQ............................................................................. – 0.3 to + 4.6 V
Power dissipation....................................................................................................................... 1 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operation and Characteristics for LV-TTL Versions
TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Input high voltage
VIH
2.0
Input low voltage
VIL
– 0.3
Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
Output low voltage (IOUT = 2.0 mA)
VOL
–
Input leakage current, any input
II(L)
–5
(0 V < VIN < VDDQ, all other inputs = 0 V)
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
–5
VCC + 0.3
0.8
–
0.4
5
5
Unit Notes
V
1, 2
V
1, 2
V
3
V
3
µA
µA
Notes
1. All voltages are referenced to VSS.
2. VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to
-2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude
measured peak to DC reference.
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Values
Unit
min.
max.
Input capacitance (CLK)
CI1
2.5
4.0
pF
Input capacitance
CI2
2.5
5.0
pF
(A0 - A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
Input/Output capacitance (DQ)
CIO
4.0
6.5
pF
Semiconductor Group
15
1998-10-01