HYB39S256400 Datasheet, PDF (19/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Notes for AC Parameters
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced
to the 1.4 V crossover point. The transition time is measured between V_IH and V_IL. All AC
measurements assume t_T = 1 ns with the AC output load circuit shown in Figure 1. Specified t_AC
and t_OH parameters are measured with a 50 pF only, without any resistive termination and with
an input signal of 1 V/ns edge rate between 0.8 V and 2.0 V.
CLOCK
t _CH
2.4 V
0.4 V
t _CL
t_T
t _SETUP
t _HOLD
INPUT
1.4 V
t_AC
t _LZ
t_AC
t _OH
OUTPUT
1.4 V
t _HZ
SPT03404
Figure 1
3. AC timing test conditions for SSTL_3 versions
+_Vtt
I/O
50 pF
Measurement conditions for
t_AC and t_OH
Output
Z = 50 Ω
Figure 2
Termination voltage
Reverence Level of Output Signals (V_REF)
Output Load
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals (V_REF)
50 Ω
30 pF
SPS03410
0.45 × V_CCQ
0.45 × V_CCQ
see Figure 2
1 ns
0.45 × V_CCQ
Semiconductor Group
19
1998-10-01