HYB39S256400 Datasheet, PDF (7/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity Function
CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are
Edge sampled on the rising edge of the clock.
CKE
Input
Level Active
High
Activates the CLK signal when high and deactivates the CLK
signal when low, thereby initiates either the Power Down
mode, Suspend mode, or the Self Refresh mode.
CS
Input Pulse Active CS enables the command decoder when low and disables
Low
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse Active
Low
When sampled at the positive rising edge of the clock, CAS,
RAS, and WE define the command to be executed by the
SDRAM.
A0 - Input Level –
A12
During a Bank Activate command cycle, A0 - A12 defines the
row address (RA0 - RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0 - An defines the
column address (CA0 - CAn) when sampled at the rising
clock edge. CAn depends from the SDRAM organization:
64M × 4 SDRAM CAn = CA9, CA11
(Page Length = 2048 bits)
32M × 8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M × 16 SDRAM CAn = CA8 (Page Length = 512 bits)
BA0
BA1
DQx
Input Level –
Input Level –
Out-
put
In addition to the column address, A10 (= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
Bank Select (BS) Inputs. Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
Semiconductor Group
7
1998-10-01