HYB39S256400 Datasheet, PDF (38/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
12.2. Clock Suspension During Burst Read CAS Latency = 3
Burst Length = 4, CAS Latency = 3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t _CK3
CKE
CS
RAS
CAS
WE
BS
AP
RAx
Addr.
RAx
CAx
DQM
t _CSL
t _CSL
t _CSL
t _HZ
Hi-Z
DQ
Ax0 Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock
Suspend
1 Cycle
Clock
Suspend
2 Cycles
Clock
Suspend
3 Cycles
SPT03915
Semiconductor Group
38
1998-10-01