HYB39S256400 Datasheet, PDF (17/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
AC Characteristics ^{1, 2, 3}
T_A = 0 to 70 °C; V_SS = 0 V; V_DD = 3.3 V ± 0.3 V, t_T = 1 ns
Parameter
Symb.
Limit Values
Unit Note
-8
-8B
-10
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3 _tCK
CAS Latency = 2
Clock Frequency
CAS Latency = 3 _tCK
CAS Latency = 2
Access Time from Clock
CAS Latency = 3 _tAC
CAS Latency = 2
Clock High Pulse Width
t_CH
Clock Low Pulse Width
t_CL
Transition time
t_T
Setup and Hold Times
Input Setup Time
t_IS
Input Hold Time
t_IH
CKE Setup Time
t_CKS
CKE Hold Time
t_CKH
Mode Register Setup time
t_RSC
Power Down Mode Entry Time t_SB
Common Parameters
Row to Column Delay Time t_RCD
Row Precharge Time
t_RP
Row Active Time
t_RAS
Row Cycle Time
t_RC
Activate (a) to Activate (b)
t_RRD
Command period
CAS (a) to CAS (b)
t_CCD
Command period
8 – 10 – 10 – ns
10 – 12 – 15 – ns
– 125
– 100
100 –
83 –
100 MHz
66 MHz
2, 4
–6
–6
6 – 7 ns
7 – 8 ns
3 – 3 – 3 – ns
3 – 3 – 3 – ns
0.5 10 0.5 10 0.5 10 ns
2–
1–
2–
1–
16 –
08
2
–
2.5 –
ns ⁵
1
–
1
–
ns ⁵
2
–
2.5 –
ns ⁵
1
–
1
–
ns ⁵
20 – 20 – ns
0 10 0 10 ns
20 –
20 –
30 –
ns ⁶
20 –
30 –
30 –
ns ⁶
50 100k 60 100k 60 100k ns ⁶
70 –
80 –
90 –
ns ⁶
16 –
20 –
20 –
ns ⁶
1 – 1 – 1 – CLK
Semiconductor Group
17
1998-10-01