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HYB39S256400 Datasheet, PDF (30/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM | |||
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HYB 39S256400/800/160T
256 MBit Synchronous DRAM
6. Write and Read Interrupt
6.1. Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Write B NOP NOP NOP NOP NOP NOP
1 Clk Interval
DQâs
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
6.2. Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Read B NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t CK2, DQâs
CAS
latency = 3
t CK3, DQâs
DIN A0 donât care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0 donât care donât care
Input data for the Write is ignored.
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQâs
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
SPT03719
Semiconductor Group
30
1998-10-01
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