HYB39S256400 Datasheet, PDF (4/56 Pages) Siemens Semiconductor Group – 256 MBit Synchronous DRAM

HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column
Address Counter
Column Addresses
A0 - A9, A11, AP
BA0, BA1
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
Row
Decoder
Memory
Array
Bank 0
8196 x
2048 x
4 Bit
Row
Decoder
Memory
Array
Bank 1
8196 x
2048 x
4 Bit
Row
Decoder
Memory
Array
Bank 2
8196 x
2048 x
4 Bit
Row
Decoder
Memory
Array
Bank 3
8196 x
2048 x
4 Bit
Input Buffer Output Buffer
DQ0 - DQ3
Control Logic & Timing Generator
*) on SSTL versions only
CLK CKE CS RAS CAS WE DQM V_REF*)
SPB03781
Block Diagram for 64 M × 4 SDRAM (13/11/2 addressing)
Semiconductor Group
4
1998-10-01