GS4911B Datasheet, PDF (99/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Video_Control
VID_STD[5:0]
Clocks_Per_Line
Clocks_Per_Hsync
Hsync_To_SAV
Hsync_To_EAV
Address
4Ch
4Ch
4Ch
4Ch
4Ch
4Dh
4Dh
4Eh
4Fh
50h
51h
Bit
15-5
4
3-2
1
0
15-6
5-0
15-0
15-0
15-0
15-0
Description
R/W
Reserved. Set these bits to zero when writing to
–
4Ch.
10FID_F_pulse - set this bit HIGH to stretch the 10FID R/W
pulse duration from 1 line to 1 field.
Reference: Section 3.8.1 on page 67
Reserved. Set these bits to zero when writing to
–
4Ch.
Host_VID_STD - set this bit HIGH to select the
R/W
output video standard using register 4Dh instead of
the external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference: Section 1.4 on page 20
Reserved. Set this bit to zero when writing to 4Ch. –
Reserved. Set these bits to zero when writing to
–
4Dh.
Replaces the external VID_STD[5:0] pins when
R/W
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference: Section 1.4 on page 20
Contains the number of output video clock cycles
R/W
per line for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing
signals. Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
Contains the number of output video clock cycles in R/W
the active H Sync interval for the selected output
timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing
signals. Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
Contains the number of output video clock cycles
R/W
from the start of H Sync to the start of active video
for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing
signals. Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
Contains the number of output video clock cycles
R/W
from the start of H Sync to the end of active video
for the selected output timing format.
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing
signals. Otherwise, this register is read-only.
Reference: Section 3.10 on page 74
Default
–
0
–
0
–
–
00h
–
–
–
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
99 of 119