GS4911B Datasheet, PDF (35/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 2-2: AC Electrical Characteristics (Continued)
V_DD = 1.8V, T_A = 0°C to 70°C, unless otherwise specified.
Parameter
Symbol
Condition
Min
Typ
Max
Units Notes
GSPI Input Hold Time
t₈ in
–
Figure 3-18
1.5
–
–
ns
7
NOTES
1. The video output clock may be directly connected to Gennum’s GS1532 or GS1531 serializer for a SMPTE-compliant SDI or HD-SDI output with
output jitter below 0.2UI, when the serializer is configured for a loop bandwidth of 100KHz.
2. All SD standards EXCEPT VID_STD[5:0] = 1 (450ps typ.) and VID_STD[5:0] = 5 or 6 (500ps typ.)
3. All HD and Graphics standards EXCEPT VID_STD[5:0] = 22 (300ps typ.) and VID_STD[5:0] = 41-43 (400ps typ.)
4. Timings from any CLK output to any other CLK output.
5. If fs=96kHz and ACLK is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typically have a 33% duty cycle distortion. See
Section 3.7.2 on page 63.
6. With PCLK phasing delay set to nominal (zero offset), each increment of the clock phasing adjustment decreases output hold time and delay
time by a nominal 700ps. The times t_OD and t_OH are defined in Figure 2-1.
7. For detailed GSPI timing parameters, please refer to Table 3-12.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
35 of 119