GS4911B Datasheet, PDF (109/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Ext_Audio_Mode
Ln_Count_Reset
Address
81h
83h
83h
Bit
15-0
15
14-0
Description
R/W
Set this register to 20C1h to enable the Extended
R/W
Audio Mode of the device.
To fully enable this mode, VID_STD[5:0] must be set
to 4d, and the F_Lock_Mask and V_Lock_Mask bits
[4:3] of register address 16h must be set to 1.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 16h.
Reference: Section 3.11 on page 75
Toggle this bit to reset the line-based counters in
R/W
the device.
This is only required when locking the “f/1.001” HD
output standards to the 525-line SD input reference
standards, or vice-versa, AND:
1. The reference has been removed and subsequently
re-applied. In this case, the user should wait until the
reference has been re-detected by the device, which
may take up to 4 frames. See Section 3.5.3 on page
47.
OR
2. The device is locked to blanking signals from a
deserializer, and the SDI input to the deserializer has
been switched upstream from the system. See
Section 3.6.5 on page 60.
Reserved. Set these bits to zero when writing to
–
83h.
Default
0
0
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
109 of 119