GS4911B Datasheet, PDF (59/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

where:
BW = the desired video PLL loop bandwidth
JITTERIN = Jitter present on applied HSYNC reference signal, in seconds
H_Feedback_Divide = the numerator of the video PLL divide ratio
H_Feedback_Divide represents the numerator of the ratio of the output clock frequency
to the frequency of the H reference pulse. It is calculated as described in Section 3.6.2.1
on page 54.
NOTE: The bandwidth calculation represented by the above equation is only
approximate. As the programmed value of Video_Res_Genlock becomes larger, the
approximation becomes more accurate.
For example, the following steps are necessary to program a loop bandwidth of 25Hz
given the following conditions: input HSYNC jitter = 3 ns, VID_STD[5:0] = 3 and input
reference format = NTSC.
1. Calculate H_Feedback_Divide (as defined in Section 3.6.2.1 on page 54):
-^H----^_---^F----^e---^e--^d---^b---^a---^c---^k---^_---^D----ⁱ-^v---ⁱ--^d---^e- × -^f--^p---^c---^l-^k---^o----^u---^t
H_Reference_Divide f_Hrefin
f_pclkout = 27MHz
∴-^H----^_---^F----^e---^e--^d---^b---^a---^c---^k---^_---^D----ⁱ--^v--ⁱ--^d---^e-
H_Reference_Divide
=
27
×
1---7---1---6--
27
=
1---7---1----6-
1
f_Hrefin
=
---2---7-----
1716
MH
z
Therefore, H_Feedback_Divide = 1716.
2. Calculate the value for Video_Res_Genlock:
Video_Res_Genlock = 47 + log₂(6 × 25 × (3 × 10^–9) × 1716) = 37
3. Calculate the value for Video_Cap_Genlock:
Video_Cap_Genlock = 37 – 21 = 16
Therefore, program Video_Res_Genlock = 37 and Video_Cap_Genlock = 16.
NOTE: The value programmed in the Video_Res_Genlock register must be between 32
and 42. The value programmed in the Video_Cap_Genlock register must be greater than
10. These limits define the exact range of loop bandwidth adjustment available.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
59 of 119