GS4911B Datasheet, PDF (94/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
ASR_SEL[2:0]
(GS4911B only)
N_a
(GS4911B only)
D_a
(GS4911B only)
RSVD
Audio_Cap_Genlock
(GS4911B only)
Audio_Res_Genlock
(GS4911B only)
Address
32h
32h
34h-33h
36h-35h
37h - 38h
39h
39h
3Ah
3Ah
Bit
15-3
2-0
31-0
31-0
–
15-6
5-0
15-6
5-0
Description
R/W
Reserved. Set these bits to zero when writing to
–
32h.
Replaces the external ASR_SEL[2:0] pins when
R/W
Host_ASR_Select (bit 2 of address 31h) is HIGH.
The default setting of this register corresponds to
an audio sample rate of 48kHz.
Reference: Section 3.7.2 on page 63
A non-zero number programmed in this register
R/W
defines the numerator for the ratio of the audio
clock to the 27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary
depending on the output audio rate selected.
Address 33h = bits 15-0
Address 34h = bits 31-16
Reference: Section 3.9.2 on page 73.
A non-zero number programmed in this register
R/W
defines the denominator for the ratio of the audio
clock to the 27MHz reference.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 31h.
The default value of this register will vary
depending on the output audio rate selected.
Address 35h = bits 15-0
Address 36h = bits 31-16
Reference: Section 3.9.2 on page 73.
Reserved.
–
Reserved. Set these bits to zero when writing to
–
39h.
Control signal to adjust loop bandwidth of audio
R/W
genlock block.
The value programmed in this register must be
between 10 and Audio_Res_Genlock - 21.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference: Section 3.6.4 on page 58
Reserved. Set these bits to zero when writing to
–
3Ah.
Control signal to adjust loop bandwidth of audio
R/W
genlock block.
The value programmed in this register must be
between 32 and 42.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference: Section 3.6.4 on page 58
Default
–
011b
–
–
–
–
–
–
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
94 of 119