GS4911B Datasheet, PDF(92/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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GS4911B Datasheet, PDF (92/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

PCLK3_Phase/Divide

PCLK3_Tristate

RSVD

Address

2Eh

2Fh

2Fh - 30h

Bit

15-6

5-2

15-2

1-0

Description

R/W

Reserved. Set these bits to zero when writing to

2Eh.

PCLK3_Phase - adjusts the output phase of the

R/W

PCLK3/PCLK3 clock with respect to the timing

output pins. Phase is delayed in 700ps (nominal)

increments as shown in Table 3-6.

Reference: Section 3.7.1 on page 61

Divide_By_4 - set this bit HIGH to divide the output R/W

PCLK3/PCLK3 by four.

Setting this bit and bit 0 simultaneously HIGH will

give the full rate video clock on the PCLK3 / PCLK3

pins.

Reference: Section 3.7.1 on page 61

Divide_By_2 - set this bit HIGH to divide the output R/W

PCLK3/PCLK3 by two.

Setting this bit and bit 1 simultaneously HIGH will

give the full rate video clock on the PCLK3 / PCLK3

pins.

Reference: Section 3.7.1 on page 61

Reserved. Set these bits to zero when writing to

2Fh.

Set these bits to 11b to tristate the PCLK3 / PCLK3

R/W

pins.

Reference: Section 3.7.1 on page 61

Reserved.

Default

00b

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

92 of 119

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