GS4911B Datasheet, PDF (13/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
27, 25, 24, VID_STD[5:0]
23, 22, 21
26, 44
CORE_VDD
28, 29, 30
ACLK1
ACLK2
ACLK3
(GS4911B only)
32, 33, 34
NC
(GS4910B only)
ASR_SEL[2:0]
(GS4911B only)
ANALOG_GND
(GS4910B only)
Timing
Type Description
Non
Input
Synchronous
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Video Standard Select.
Used to select the desired video/graphic display format for video
clock and timing signal generation.
8 different video and 13 different graphic sample clocks, as well as
35 different video format and 13 different graphic format timing
signal outputs may be selected using these pins.
For details on the supported video standards and video clock
frequency selection, please see Section 1.4 on page 20.
–
Power Most positive power supply connection for the digital core. Connect
Supply to +1.8V DC.
–
Output CLOCK SIGNAL OUTPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio output clock signals.
ACLK1, ACLK2, and ACLK3 present audio sample rate clock outputs
to the application layer.
By default, after system reset, the audio clock output pins of the
device provide clock signals as follows:
ACLK1 = 256fs
ACLK2 = 64fs
ACLK3 = fs, where fs is the fundamental sampling frequency.
The fundamental sampling frequency is selected using
ASR_SEL[2:0]. Additional sampling frequencies may be programmed
in the host interface.
It is also possible to select different division ratios for each of the
audio clock outputs by programming designated registers in the
host interface. Clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs,
64fs, fs and z bit are selectable on a pin-by-pin basis.
NOTE: ACLK1-3 will have a 50% duty cycle, unless fs is selected as
96kHz and the host interface is configured such that one of the
three ACLK pins is set to output a clock signal at 192fs or 384fs. If
this is the case, then a 512fs clock will have a 33% duty cycle.
These signals will be high impedance when ASR_SEL[2:0] = 000b.
–
–
Do not connect.
Non
Input
Synchronous
–
Power
Supply
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio Sample Rate Select.
Used to select the fundamental sampling frequency, fs, of the audio
clock outputs. See Table 3-7.
When ASR_SEL[2:0] = 000b, audio clock generation will be disabled
and the ACLK1 to ACLK3 pins will be high impedance. In this case,
AUD_PLL_VDD (pin 14) may be connected to GND to minimize noise
and power consumption.
Ground connection for the analog input block. Connect to GND.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
13 of 119