GS4911B Datasheet, PDF (85/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Output_H_Reset
Output_FV_Reset
Frame_Divider_Reset
Address
17h
18h
19h
19h
19h
Bit
15-0
15-0
15-2
1
0
Description
R/W
When the output is genlocked to the input, the
R/W
input reference is used to reset the line-based
counter controlling the generated timing output
signals.
Programming this register to a non-zero value will
over-ride the internal pixel-based counter. The
counter reset will occur every Output_H_Reset lines
instead of on a frame basis.
This register is programmed when manually
programming the internal video genlock block.
The default value of this register will vary
depending on the output video standard selected.
Reference: Section 3.6.2 on page 54
When the output is genlocked to the input, the
R/W
input reference is used to reset the frame-based
counter controlling the generated timing output
signals.
Programming this register to a non-zero value will
over-ride the internal frame-based counter. The
counter reset will occur every Output_FV_Reset
input frames.
This register is programmed when manually
programming the internal video genlock block.
NOTE: Once this register is programmed, it must be
updated using register 19h.
The default value of this register will vary
depending on the output video standard selected.
Reference: Section 3.6.2 on page 54
Reserved. Set these bits to zero when writing to
–
19h.
Ref_F_Sync - when Ref_F_Mode (bit 0 of 19h) is set R/W
HIGH, this bit is used to initialize the frame-based
counter reset programmed in 18h.
The reset pulse is generated if this bit is pulsed
(LOW to HIGH to LOW) during the output frame
immediately prior to the frame the reset is to occur.
This register is programmed when manually
programming the internal video genlock block.
Reference: Section 3.6.2 on page 54
Ref_F_Mode - set this bit HIGH to initialize the
R/W
frame-based reset via the host interface (using bit 1
above).
Reference: Section 3.6.2 on page 54
Default
–
–
–
0
0
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
85 of 119