GS4911B Datasheet, PDF (29/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 1-3: Output Timing Signals (Continued)
Signal Name
Display Enable
Audio Frame Sync
(GS4911B only)
USER_1~4
Description
Default Output Pin
The Display Enable (DE) signal is used to indicate the display enable for
graphic display interfaces.
This signal will be HIGH (default polarity) whenever pixel information is to
be displayed on the display device (i.e. whenever both H Blanking and V
Blanking are in the active video state)
The width and timing of this signal will be determined by the timing
parameters of the selected video standard (see Table 1-2), or according to
custom timing parameters programmed in the host interface (see
Section 3.10 on page 74).
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.12.3 on
page 79).
TIMING_OUT_8
The Audio Frame Sync (AFS) signal is HIGH (default polarity) for the
–
duration of the first line of the n’th video frame to indicate that the ACLK
dividers are reset at the start of line 1 of that frame. It is defined
according to the frame rate of the video format and the selected audio
sample rate programmed via the VID_STD[5:0] and ASR_SEL[2:0] pins or
the host interface.
For example, if the video format is based on a 59.94Hz frame rate and the
audio sample rate clock is 48kHz, then n=5, and the AFS signal will be
identical to the 10FID signal.
By default, the AFS signal is reset by the 10 Field Identification (10FID)
reference input. This feature may be disabled using the Audio_Control
register at address 31h of the host interface (see Section 3.12.3 on page
79). The AFS signal may also be reset using register 1Ah of the host
interface. With no reference, the frame divide by “n” controlling the AFS
signal will free-run at an arbitrary phase.
The default polarity of this signal may be inverted by programming the
Polarity register at address 56h of the host interface (see Section 3.12.3).
Please see Section 3.8.2 on page 68 for more detail on the AFS output
signal.
The GS4911B/GS4910B offers four user programmable output signals. Each –
USER signal is controlled by four timing registers and a polarity select bit.
The timing registers define the start and stop times in H pixels and V lines
and begin at address 57h of the host interface (see Section 3.12.3 on page
79).
Each user signal is individually programmable and the polarity, position,
and width of each output may be defined with respect to the H, V, and F
output timings of the device. Each output signal may be programmed in
both the horizontal and vertical dimensions relative to the leading edges
of H and V Sync. If desired, the pulses produced may then be combined
with a logical AND, OR, or XOR function to produce a composite signal
(for example, a horizontal back porch pulse during active lines only, or the
active part of lines 15 through 20 for vertical information retrieval). Each
output has selectable polarity.
Please see Section 3.8.3 on page 69 for more detail on the USER_1~4
output signals.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
29 of 119