GS4911B Datasheet, PDF (60/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.6.4.2 Loop Bandwidth of the Audio PLL (GS4911B only)
The capacitive component of the filter controlling the audio loop bandwidth is
determined by the Audio_Cap_Genlock register and the resistive component is
determined by the Audio_Res_Genlock register. These two registers are located at
addresses 39h and 3Ah, respectively, of the host interface.
To determine the setting of Audio_Res_Genlock and Audio_Cap_Genlock, the following
equations must be solved:
Audio_Res_Genlock = 47 + log₂(6 × BW × JITTERIN × A _Feedback_Divide )
Audio_Cap_Genlock ≤ Audio_Res_Genlock – 21
where:
BW = the desired audio PLL loop bandwidth
JITTERIN = Jitter present on output PCLK, in seconds.
A_Feedback_Divide = the numerator of the audio PLL divide ratio
A_Feedback_Divide is calculated in the same way as demonstrated in Section 3.6.2.2 on
page 56.
NOTE: The bandwidth calculation represented by the above equation is only
approximate. As the programmed value of Audio_Res_Genlock becomes larger, the
approximation becomes more accurate.
NOTE2: The value programmed in the Audio_Res_Genlock register must be between 32
and 42. The value programmed in the Audio_Cap_Genlock register must be greater than
10. These limits define the exact range of loop bandwidth adjustment available.
3.6.5 Locking to Digital Timing from a Deserializer
As described in Section 3.4.1 on page 43, the GS4911B/GS4910B may be genlocked to
either an analog reference, such as a Black & Burst signal, or to an SDI input via the
digital H, V, and F blanking signals normally produced by a deserializer. When locking
to an SDI input, the user should consider the possibility of a switch of the SDI signal
upstream from the system.
If the GS4911B/GS4910B is locked to the digital H, V, and F blanking signals produced
by a deserializer, and the SDI input to the deserializer is switched such that the phase of
the H input changes abruptly, the REF_LOST output will remain LOW and the
GS4911B/GS4910B will not crash lock to the new H phase. Instead, the clock and timing
outputs will very slowly drift towards the new phase. During this period of drift, the
LOCK_LOST output will be LOW, even though the device is not genlocked.
The user should clear the Run_Window bits [2:0] of register address 24h to force the
device to crash lock should such a switch occur. This will cause the GS4911B/GS4910B
to crash lock whenever it sees a disturbance of the input H signal.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
60 of 119