GS4911B Datasheet, PDF (111/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Application HOST
GS4911B/GS4910B
CS_TMS
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
Tri-State
In-circuit ATE probe
JTAG/HOST
Figure 3-20: System JTAG
NOTE: When running boundary scan testing, the TIMING_OUT_n pins should be set to
high-impedance by setting VID_STDn to 000h.
3.14 Device Power-Up
3.14.1 Power Supply Sequencing
The GS4911B/GS4910B has a recommended power supply sequence. To ensure correct
power-up, the ANALOG_VDD and CORE_VDD power pins should be powered before
IO_VDD.
Device pins may be driven prior to power-up without causing damage.
3.15 Device Reset
In order to initialize operating conditions to their default states, the application layer
must hold the RESET signal LOW during power up and for a minimum of 500us after the
last supply has reached its operating voltage.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
111 of 119