GS4911B Datasheet, PDF (17/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
49
Name
PCLK2
Timing
–
51
PCLK1
–
52
PCLK1&2_GND
–
53
PCLK1&2_VDD
–
54
PhS_VDD
–
55
PhS_GND
–
Type Description
Output
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK2 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK2 output pin will operate at
the fundamental frequency determined by the setting of the
VID_STD[5:0] pins. It is possible to define other non-standard
fundamental clock rates using the host interface.
It is also possible to select different division ratios for the PCLK2
output by programming designated registers in the host interface.
A clock output of the fundamental rate, fundamental rate ÷2, or
fundamental rate ÷4 may be selected.
By setting designated registers in the host interface, the current
drive capability of this pin may be set high or low. By default, the
current drive will be low. It must be set high if the clock rate is
greater than 100MHz.
The PCLK2 output will be held LOW when VID_STD[5:0] = 00h.
Output
CLOCK SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK1 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK1 output pin will operate at
the fundamental frequency determined by the setting of the
VID_STD[5:0] pins. It is possible to define other non-standard
fundamental clock rates using the host interface.
It is also possible to select different division ratios for the PCLK1
output by programming designated registers in the host interface.
A clock output of the fundamental rate, fundamental rate ÷2, or
fundamental rate ÷4 may be selected.
By setting designated registers in the host interface, the current
drive capability of this pin may be set high or low. By default, the
current drive will be low. It must be set high if the clock rate is
greater than 100MHz.
The PCLK1 output will be held LOW when VID_STD[5:0] = 00h.
Power Ground connection for PCLK1&2 circuitry. Connect to GND.
Supply
Power Most positive power supply connection for PCLK1&2 circuitry.
Supply Connect to +1.8V DC.
Power Most positive power supply connection for the video clock phase
Supply shift internal block. Connect to +1.8V DC.
Power Ground connection for the video clock phase shift internal block.
Supply Connect to GND.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
17 of 119