GS4911B Datasheet, PDF (72/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.8.4.1 Selectable Current Drive and Polarity
The current-drive of each timing output pin is also selectable via the Output_Select
registers. The current drive of each TIMING_OUT pin is low by default. However, it may
be set high to accommodate certain applications.
Additionally, the Polarity register of the host interface may be programmed to select the
polarity of each timing output signal.
3.9 Custom Clock Generation
In addition to the device’s pre-programmed clock frequencies, the user may generate a
custom audio or video clock by programming designated registers in the host interface.
Custom video clock generation is supported by both the GS4910B and GS4911B and is
described in Section 3.9.1 on page 72. Custom audio clock generation is only supported
by the GS4911B and is described in Section 3.9.2 on page 73.
3.9.1 Programming a Custom Video Clock
The fundamental frequency of the video clock is defined by the output video format
initially set by VID_STD[5:0]. At any time, this fundamental frequency may be modified
to create a custom output video format.
The user may generate a video clock with any frequency between 13.5MHz and
165MHz. By programming the PCLK_Divide registers, the output PCLK may be as low as
13.5/4 = 3.375MHz.
Generating a custom video clock will change the period of the video timing signals
presented to the TIMING_OUT pins; however, the pixels per line, lines per frame, and
other pixel and line-based timing signals will remain unchanged. To redefine the pixel
and line based timing parameters, registers 4Eh to 55h must be reprogrammed as
described in Section 3.10 on page 74.
The frequency of the custom video clock is determined using a ratio based on the 27MHz
reference. Therefore, to program a custom clock, the user must calculate and program
the set of integers (N_v, D_v) in the equation:
N_{-----v- =} f_{---o---u----t}
D_v f_in
where:
f_out = desired output video clock frequency
f_in = 27MHz crystal reference
N_v = numerator of the ratio (host register 20h-21h)
D_v = denominator of the ratio (host register 22h-23h)
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
72 of 119