GS4911B Datasheet, PDF (79/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

t5
SCLK
CS
SDIN
R/W RSV RSV AutoInc A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDOUT
R/W
RSV RSV AutoInc A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 3-17: GSPI Read Mode Timing
t6
D15 D14 D13 D12 D11 D10 D9
D8 D7
D6
D5
D4
D3
D2
D1
D0
t0
t1
t4
t7
SCLK
t3
CS
t2
t8
SDIN R/W RSV RSV AutoInc A11 A10
A9
A8
A7
A6
A5
A4 A3
A2
A1
A0
SDOUT _{R/W RSV RSV AutoInc A11}
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 3-18: GSPI Write Mode Timing
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3.12.3 Configuration and Status Registers
Table 3-13 summarizes the GS4911B/GS4910B's internal status and configuration
registers.
All registers are available to the host via the GSPI and are all individually addressable.
Table 3-13: Configuration and Status Registers
Register Name
RSVD
H_Period
Address
00h - 09h
0Ah
Bit
–
15-0
Description
Reserved.
Contains the number of 27MHz pulses in the input
H Sync period. This register is set by the Reference
Format Detector block using the H Sync signal
present on the external HSYNC input pin.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a
different HSYNC period is applied.
Reference: Section 3.5.1 on page 45
R/W
–
R
Default
–
N/A
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
79 of 119