GS4911B Datasheet, PDF (39/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

• V_Offset (1Ch) - the difference between the reference VSYNC signal and the output
V Sync and/or V Blanking in lines, with a control range of zero to +1 frame. All
line-based timing output signals will be delayed by the vertical offset programmed
in this register.
The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in Table 3-1.
The offset programmed will be in the positive direction. Note that the step size will
depend on the frequency of the output video clock.
NOTE: If VID_STD[5:0] = 63 and the reference format is changed, care must be taken to
ensure that the Clock_Phase_Offset register is correctly programmed for the new output
format before the reference is applied.
Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme
VID_STD[5:0]
Setting
Output Video Clock
Frequency
Step Size
(Fraction
of a PCLK)
Maximum
Number of
Steps
Bits Required to
Set the Number
of Steps
Clock_Phase_Offset [15:0]
Settings
1
3-6, 39-42
f_PCLK < 20MHz
---1-----
512
20MHz < f_PCLK < 40MHz
---1-----
256
511
b₈b₇b₆b₅b₄b₃b₂b₁b b₈000001b₈b₇b₆b₅b₄b₃b₂b₁b₀
0
255
b₇b₆b₅b₄b₃b₂b₁b₀
b₇000010b₇b₆b₅b₄0b₃b₂b₁b₀
7-20, 25-38,
43-46
40MHz < f_PCLK < 80MHz
---1-----
128
127
b₆b₅b₄b₃b₂b₁b₀
b₆000100b₆b₅b₄00b₃b₂b₁b₀
21-23, 47-51
f_PCLK > 80MHz
--1---
64
63
b₅b₄b₃b₂b₁b₀
b₅001000b₅b₄000b₃b₂b₁b₀
Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset.
The value programmed in the H_Offset register (1Bh) must not exceed the maximum
number of clock periods per line of the outgoing video standard. Similarly, the value
programmed in the V_Offset register (1Ch) must not exceed the maximum number of
lines per frame of the outgoing standard. Both horizontal and vertical offsets will be in
the positive direction. Negative offsets (advances) are achieved by programming a value
in the appropriate register equal to the maximum allowable offset minus the desired
advance.
NOTES:
1. The device will delay all output timing signals by 2 PCLKs relative to the input
HSYNC reference. This will occur even when the H_Offset register is not
programmed. The user may compensate for this delay by subtracting 2 PCLK cycles
from the desired horizontal offset before loading the value into the host interface.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
39 of 119