GS4911B Datasheet, PDF(93/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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GS4911B Datasheet, PDF (93/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

Audio_Control

(GS4911B only)

Address

31h

Bit

15-10

9-7

4-3

Description

R/W

Reserved. Set these bits to zero when writing to

31h.

AFS_Reset_Window - These bits may be used to

R/W

adjust the value by which the audio clock counters

are allowed to drift from the output AFS pulse.

The encoding scheme for this register is shown in

Table 3-9.

NOTE: The default setting of this register will

provide a reset window that is sufficient for most

standards. To maintain correct audio clock

frequencies for some VESA standards, the reset

window may have to be increased from its default

setting. In this case, set the value of this register to

1XX. See Table 3-9.

Reference: Section 3.7.2 on page 63

Update_Custom_A_Clock - this bit is used to update R/W

the custom audio clock parameters programmed in

registers 33h to 36h of the host interface. All

non-zero parameters in these registers will be

updated via a LOW to HIGH transition on this bit.

Enable_384fs - set this bit HIGH to enable the 384fs R/W

and 192fs audio clock outputs. This must be set in

addition to registers 3Fh to 41h.

NOTE: If this bit is HIGH, then a 512fs audio clock

will have a 33% duty cycle when fs = 96kHz.

Reference: Section 3.7.2 on page 63

Reserved. Set these bits to zero when writing to

31h.

Host_ASR_SEL - set this bit HIGH to select the audio R/W

sample rate using register 32h instead of the

external ASR_SEL[2:0] pins.

The external ASR_SEL[2:0] pins will be ignored, but

should not be left floating.

Reference: Section 3.7.2 on page 63

AFS_F_Pulse - set this bit to 1 to stretch the AFS

R/W

pulse duration from 1 line to 1 field.

Reference: Section 3.8.2 on page 68

AFS_Reset_Disable - set this bit HIGH to disable the R/W

10FID input reference pin from resetting the output

AFS pulse. If this bit is set HIGH, the output AFS

pulse will free-run or may be reset using register

1Ah. The external 10FID pin should not be left

floating.

Reference: Section 3.8.2 on page 68

Default

010b

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

93 of 119

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