GS4911B Datasheet, PDF (78/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

MSB
LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3-16: Data Word Format
3.12.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in Figure 3-17 and
Figure 3-18 respectively. The timing parameters are defined in Table 3-12.
When several devices are connected to the GSPI chain, only one CS should be asserted
during a read sequence.
During the write sequence, all command and following data words input at the SDIN pin
are output at the SDOUT pin as is. Where several devices are connected to the GSPI
chain, data can be written simultaneously to all the devices that have CS set LOW.
Table 3-12: GSPI Timing Parameters
Parameter
t₀
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
Definition
Specification
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
The minimum SCLK period.
1.5 ns
100 ns
Duty cycle tolerated by SCLK.
40% to 60%
Minimum input setup time.
1.5 ns
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word (write
cycle).
The minimum duration of time between the last SCLK
command word (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word (read
cycle).
Minimum output hold time (15pF load).
37.1 ns
148.4 ns
1.5 ns
The minimum duration of time between the last SCLK
of the GSPI transaction and when CS can be set HIGH.
Minimum input hold time.
37.1 ns
1.5 ns
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
78 of 119