GS4911B Datasheet, PDF (63/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.7.2 Audio Clock Synthesis (GS4911B only)
The programmable audio clock generator is referenced to the internal PCLK signal and
is responsible for generating the ACLK output signals. Three audio clock output pins,
ACLK1 to ACLK3, are available to the application layer.
The fundamental sampling frequency, fs, is selected using the ASR_SEL[2:0] pins as
shown in Table 3-7. Once selected, the audio clock rate may be customized via the host
interface (see Section 3.9 on page 72).
If desired, the external ASR_SEL[2:0] pins may be ignored by setting bit 2 of the
Audio_Control register and the sampling frequency may instead be programmed in the
ASR_SEL[2:0] register of the host interface (see Section 3.12.3 on page 79). Although the
external ASR_SEL[2:0] pins will be ignored, they should not be left floating.
Table 3-7: Audio Sample Rate Select
ASR_SEL[2:0]
Sampling Frequency (kHz)
000
Audio Clock Generation Disabled
001
32
010
44.1
011
48
100
96
101
Slow 32*
110
Slow 44.1*
111
Slow 48*
*Slow 32, 44.1, and 48 are available only when the video standard selected is 23.98, 29.97, or
59.94 frame rate based. They refer to 32kHz, 44.1kHz, or 48kHz multiplied by 1000/1001 to
maintain the 1, 2, or 3 frame sequence normally associated with 24, 30, and 60 fps video.
When all three ASR_SEL[2:0] pins are set LOW, the audio clock outputs will be high
impedance. In this case, the application layer may continue to power the
AUD_PLL_VDD pin; however, to minimize noise and power consumption,
AUD_PLL_VDD may be grounded.
By default, after system reset, ACLK1 to ACLK3 will output clock signals at 256fs, 64fs,
and fs respectively. Different division ratios for each output pin may be selected by
programming the ACLK_fs_Multiple registers beginning at address 3Fh of the host
interface (see Section 3.12.3 on page 79). The encoding of this register is shown in
Table 3-8. Clock outputs of 512fs, 348fs, 256fs, 192fs, 128fs, 64fs, fs, and z bit are
selectable on a pin by pin basis. The z bit will go HIGH for one fs period every 192 fs
periods. Its phase is not defined by any timing event in the GS4911B, and so is arbitrary.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
63 of 119